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Manufacturers of semiconductor components repeatedly report on the benefits of vias for heat dissipation, also called thermal via: Thermovias are mechanically drilled vias from TOP to BOTTOM. Ideally, vias are placed directly under the components and exclusively intended for heat dissipation.

Usually, Manufacturers provide general recommendations for guidance respectively ideal dimensions and distances of these thermovias. However, these guidelines, mostly referring to the demoboard of the respective manufacturer, do not consider the fact that in this way no generally valid statement can be made for all designs. The design of the board and its size as well as the number of layers affect the validity of the recommendations quite substantially. So, the decision concerning the number of thermovias should always be made on an individual basis. Furthermore, it should be taken into account that a larger number of thermovias cannot "dissipate" more heat, even though time and costs increase proportionally. Instead, it is more important to find a appropriate number of vias which balances benefits and costs.

This raises the question: How do you obtain a result that really works for your printed circuit board? How many thermal vias are practically feasible in terms of manufacturing effort and costs?

The experimental effort needed to determine the ideal number for any given design would be excessive. Excel sheets that "calculate" the thermal resistance of n-pieces of thermal via would be even impractical. Merely a simulation program can provide a meaningful graph for temperature vs. number of holes in a short time at low cost.

PCB-Investigator Physics is a simulation tool that is able to reproduce the design status of any circuit board in detail and therefore allows you to explore the possibilities of thermal vias. The layer stackup, the schematic and the drilling scheme are imported from ODB++/IPC2581 data and can subsequently be used for the thermal simulation. Both vias and plated micro vias can be used for the drilling process. In addition, thermal data such as the thermal conductivity of FR4, the temperature and the state of motion of the surrounding air are required - with Physics all parameters can be set and adjusted in a few minutes. If you play around with the pitch, number and arrangement of the thermovias, you can predict a reasonable prototype that will not cause any problems in production regarding its thermal behavior.

Let us illustrate these deliberations by using a concrete example. In a 2-layer board (Fig. 1) there is a heat-critical component. We wish to control the temperature of this component with the help of thermal vias and/or cause a reduction in temperature.

Fig. 1: Example for the thermal analysis with PCB-Investigator Physics. Thermal vias will be drilled under the large black IC to ensure improved heat dissipation.


For simplification, a basic layer stack-up was chosen. However, there are no restrictions when using PCB-Investigator regarding potential multilayer boards.

The simulation program PCB-Investigator Physics automatically creates a physical calculation model based on the geometry data, which takes into account both the heat conduction within the board and the heat transfer to the ambient air. As for all 3D field solvers, the calculation time will vary depending on the number of nodes and the convergence speed, as the calculation is transferred in an iterative loop from cold to heated state. To speed up the computation, PCB-Investigator Physics uses the graphics processor (GPU) to increase the time per iteration significantly in comparison to the CPU. Reliable results can thus be delivered in just a few minutes.

The simulation result for the sample board without thermovias is shown in Fig. 3. The temperature of the component is 103.4°C without vias.

Fig. 3.1: Simulation results (3D) of the printed circuit board without thermovias.


Fig. 3.2: Simulation result of the top side (102.1°C) and bottom side (65.5°C) without any microvias.


Using 15 thermal vias arranged in a regular pattern, the following image emerges (Fig.4.). The temperature of the component is substantially lower due to the heat dissipation of the vias, reaching 83.9°C.

Fig. 4.1: 3D view of the circuit board with 15 thermovias. The orange color of the component indicates a considerable cooling of the component.

Fig. 4.2: Simulation result of the top side (82.0°C) and bottom side (69.1°C) with 15 thermovias (visible as green dots).


Besides the thermal vias, there are also other factors that play a decisive role for heat dissipation and must therefore be included in the thermal management considerations of the PCB. On the one hand, heat tends to flow into well-conducting materials, i.e. the traces, and on the other hand the heat can hardly skip the FR4 pitches between the traces (of course there is heat transport in the FR4, which is even considerable due to its volume and area). The reduction of the component temperature from about 103°C to 84°C is already enormous, especially with respect to the ambient temperature (20°C).

Let's add some more thermal vias to the simulation (Fig.5) and see the resulting heat dissipation.

Fig. 5.1: View of the printed circuit board (3D) with 170 holes.

Fig. 5.2: Simulation result of the top side (71.5°C) and bottom side (70.6°C) with 170 thermovias (visible as green dots).


The multiplication of the thermal vias has led to a considerable reduction in temperature here. The temperature of the component has now reached 72.8 °C, a reduction of about 30 °C due to a better heat dissipation.

Now, the question arises about the usefulness of further drillings, after we could already achieve such a strong cooling. However, at a certain point we can see that some kind of saturation is reached at which the temperature curve flattens out steadily, although the number of thermal vias is increased to an even greater extent. Thus, if the number of vias is quadrupled to a total of 680, a relatively small reduction in temperature to 72°C is observed, corresponding to a cooling of less than 1°C. The temperature of the bot layer is almost identical to the one of the top layer. As a result, further heat dissipation is no longer possible.

It can be concluded that at a certain number of thermal vias the utility will become less than the expense, meaning that the design should not simply be arbitrarily designed with as many drill holes as possible.

You can see this effect in the following diagram (Fig 6). It shows an increasing approximation of the graphs of the bot and top layer with regard to their maximum temperature as a function of the amount of thermal vias. Likewise, an increasing flattening of the temperature curve can be noted despite the increasing number of vias. The decline in temperature reaches the aforementioned saturation. It is caused by the convection flow on the surface of the PCB which represents a terminating thermal resistance. That resistance is unaffected by the number of thermal vias and cannot be undercut; a fan or heat sink would have to be used to lower it.

Fig. 6.1: Overview of the temperature variations depending on the quantity of thermal vias.

Fig.6.2: Parameter study. Even with an infinite number of thermovias, the component will not be colder than about 70 °C.


Depending on the application of your board, the intended housing and the expected ambient temperature, different temperature limits must be observed. These limits should be calculated preferably at the design stage of the board to avoid late and expensive modifications caused by the lack of thermal management.

PCB-Investigator Physics enables you to determine the ideal number of thermal vias for your design so that given temperature limits are not exceeded. At the same time, you can avoid additional costs and time delays caused by additional but unnecessary vias. Find out how many thermal vias your board actually needs!

Using Physics simulation, thermal vias can be planned in a time- and cost-saving way.

Even in difficult times like these, we are constantly focusing on the further development of our software in order to be able to offer you as our customer the best possible added value. We therefore now provide you the latest version 11.1 of PCB-Investigator with numerous further developments, optimizations and innovations.

For example, we have improved the AOI analysis, both the 2D and 3D ray check, to achieve even faster and more reliable simulation results.

The Panel Builder has also been further developed in numerous aspects to make it even easier for you to create panels.

Our management platform PCB-I 365, one of our latest features, is being constantly revised to increase the performance and thus increase the efficiency of your workflow.

Here is a complete list of all new features of version 11.1:

  • improved AOI 3D Ray Check and additional report function for HTML
  • accelerated AOI 2D Check and huge improvement regarding the recognition of the inspection direction
  • new filter method for AOI 2D / 3D Check: Exclusion of components not been soldered at the time of the AOI Check (e.g. THT components)
  • PCBI 365: Various improvements regarding e.g.
    • management of checked-out designs, storage of last used paths
    • performance enhancement
  • DFM analysis: More precise distance check to panel edge regarding the definition of sides (left/right/top/bottom) and the definition of values for the top/bottom side of the pcb
  • Viscom: Adaptations for AXI with laser markers (warping inspection), deactivating option for components concerning the output
  • Detailed pin information in the "Component Property" dialog
  • Hazard analysis: Possibility of defining coating layers to not report defects below coating areas
  • Improvements in Eagle Import
  • Bugfix in GenCad Import/Export
  • Operational improvements in the "Database Compare“
  • Possibilty of applying all measuring methods also between individual parts in the panel (except Net-2-Net)
  • Improvement of Excellon 1/2 + Sieb and Meyer Import
  • Improvements in the Panel Builder:
    • Performance Enhancement
    • Better measurement methods regarding the distance between two components and the distance of a component to the outline
  • New editing option: Fast conversion of the zero point to a PCB corner or a selected element (e.g. snap hole)
  • Scripting: Autostart of Scripts
  • Bare Board Analysis (DRC): New possibility of finding and reporting missing heat traps on SMD pads and THT pads (here: also inner layers) ("Missing Thermal Clearance")
  • Possibility of starting the tool Panel Optimizer from the Panel Builder
  • PDF Synchronization: „Cross-Probing" with a PDF document, e.g. PDF circuit diagram, assembly drawing (selecting in PCBI leads to the same selection in the PDF and vice versa)
  • Improved Parmi export (=machine format)
  • Better search function in the PCB-Investigator
  • Small improvement regarding the editition of part properties (when an attribute is renamed or updated simultaneously for multiple parts)
  • Various extensions of the API programming interface
  • Performance improvements of the Part Library in PCBI (including new filters/search functions for PCBI 365 libraries)
  • Docking points: additional docking points for a better drag and drop system
  • Easier handling of the selection of overlapping components

Now available: The latest version 10.5 of PCB-Investigator!

Benefit from the numerous updates and improvements of our latest PCB-Investigator Version V10.5









Overview of the most important innovations:

  • Eagle Update: improved area fill flooding / thermal tie creation
  • Database Compare Update: percent values for pins instead of components per net
  • DPF-Update: better internal attribute handling
  • GenCad Update: better error handling with invalid package names and empty text content
  • Improved graphically compare for panel
  • Improved TGZ Import: invalid file chars are now replaced by "_"
  • Dimensioning Update: better visualization of dimensions in bottom view
  • Attribut Histogramm Update: package size added for component layers
  • Component Attribute Export Update: package size added
  • If PCB and Panel are existing in a dataset, the PCB is always loaded at start-up
  • More links to the manual in different sub-windows
  • Printing Update: last used options are stored in the ini file
  • Reworked mouse wheel zoom: if sub-windows are open and overlapping the drawing area, the view is centered to the remaining part of the drawing area
  • Bugfixes: e.g. no empty file output, some missing flags for saving

The newest Version 10.3 of PCB-Investigator has been released.

You are now able to calculate critical areas with Hazard Analysis!

PCB-Investigator V10.3 offers you some new functions that will facilitate you daily work:

  • Hazard Analysis: Hazard analysis was previously only possible using distance values. Now, you can carry out a surface check following the risk assessment tool of ZVEI (for the determination of the short-circuit risk by particles). The possible danger zones can now also be displayed as an area. Examples can be found in the appendix.

  • Dimensioning Feature: With the new dimensioning feature you can now also add e.g. dimensions or notes to your design. Here, you will also find an example in the appendix.
  • H-Bridge Inspection: It defines the keepouts between the pins of a component. All areas will be reported in which copper tracks are within a barrier and are also connected to at least one of the two pins, as they might cause AOI problems.
  • TP Report updated with new options.
  • Tombstone Check with new filter options.

A printed circuit board runs through many different steps starting with its development and design to its final production.

Using PCB-Investigator Embedded Export Viewer you enable every involved person to work with PCB-Investigator without buying more licenses or running more time-consuming installations. You have no additional costs, but can easily bring everyone down to a common denominator. Choose the chargeable version Embedded plus and automate your viewer for your individual needs.

The PCB data set and the PCB-Investigator Software are saved together within one file and sent as an email attachment or exchanged via any data medium.

Every participant of the production process gets access to all necessary data and is able to work on it with a restricted full version of PCB-Investigator. Optimizing BOM management or EMC control are just two examples of how much you can profit from this special PCB-Investigator feature.

Here is an overview of all features included in the Embedded Export Viewer:

  • Search for components and display it including all attributes
  • Search function Ctrl - F
  • Top and bottom view
  • Select nets and display over single layers or all layers
  • Select single elements or a whole net
  • All measuring functions
  • Labeling of the nets with net names or conducting path thickness
  • Display all components and uses; switchable over tab
  • Notes system for the display of notes and automatic zoom to a position
  • Different color adjustments
  • Assign colors to all nets and components
  • Display the section in a layout plan
  • Metric or imperial view of units
  • Display a histogram of all parts of a layer
  • Fade in a grid as a point or line
  • Print all layers
  • supports touchscreen devices
  • No additional costs

Choose the customizable version Embedded plus and automate your viewer for your individual needs. This plus version offers you even more features than the basic Embedded Export Viewer.

Get the chargeable license of Embedded plus and benefit from the following features that will optimize the flow of information in your company to a new maximum!

  • Runnable over a batch file with specific ODB++ data
  • Linked with a PLM system data base or web request (RestFull) over a .NET interface
  • Selection by an interface, e.g. barcode scanner, ICT, AOI
  • Individual defaults for display
  • Individual color adjustment for components and nets, e.g. all polarized components in green
  • Rotation of single components for a better visualization
  • 2D and 3D view of the board including the real components
  • Live integration of pictures of a camera
  • Generate a digital first sample test report
  • Zoom controlled by external devices
  • Synchronize with machines, e.g. Boundary Scanner, ICT adapter, AOI, Flying Prob
  • Connection to a PLM system by.NET interface
  • Automatic dimension of component groups
  • Integration of an individual surface for customized tasks
  • Adaptable ribbon menu for individual requirements
  • Display of the layer structure including copper thickness and drills
  • Fade-in of information directly in the CAD Display, e.g. component rotation, drawing number
  • Includable menu for opening PDFs
  • Create screenshots with automatic storage
  • Display of solder resist masks (positive or negative)
  • Fade-in of releases or quantities
  • Display of BOM including variation

In addition to other PCB data formats like ODB++, GenCad, IPC2581, DXF, DPF, ... now, PCB-Investigator is also able to directly import your EAGLE layout without having to use any ULP program or workaround.

Just drag&drop your '.brd' file, it’s as simple as that!

To ensure further processability in e.g. DRC check or Thermal Simulation, PCB-Investigator takes over any useful data like:

  • signal, mask, paste and drill layers
  • flooded area fills
  • net names
  • components including available attributes
  • stack-up information
  • restriction areas / keepouts

Of course the read in data set can also be exported to ODB++, GenCad, Gerber, IDF, DXF, ...

In that way PCB-Investigator is also the perfect tool for data conversion between EAGLE and other data formats.

The Profile, also known as contour or outline, represents the outer edges of a printed circuit board as well as its inner recesses like drill holes. Among other things, it is prerequisite for indicating the shape of a PCB and thus being able to string several boards together on a panel. Moreover, PCB-Investigator uses it for a variety of calculations, tests, and features. These include:

  • measuring from components to outer edges
  • calculation of areas such as the amount of areas covered with copper
  • verification if PCB fits into its case
  • for displaying 3D

The contour function which can be reached through view > contour reflects the importance of the Profile and offers an overview over the entire outline network by placing the contour of the PCB in the middle of the screen with the highest zoom possible.

Given the importance of the Profile, it is no surprise that it is a fixed part of many data formats like ODB++, IPC2581 and GenCAD, but not Gerber. This is why PCB-Investigator automatically creates the Profile when importing Gerber files, but only at the first time meaning the initially created profile is not changed. Its dimensions will most likely diverge from the ones needed thus making an editing possibility vital, which is provided by the Set Profile function available at Edit > Profile.


The Set Profile function allows to clear all previously defined outlines as well as define new ones. You can either let PCB-Investigator set outlines around all elements of an active layer automatically using “Set by all Objects” or draw them freely. The easiest way to draw freely is using the rectangle selection, but you can also draw the outlines using several connected lines.

The “Add active Layer to Outline” adds the contours of all elements of the currently active layer to Profile. If there is more than one layer active the first layer of the layer stack up is used.

“Add Selection to Outline” allows you to add the outline of the currently active selection to the Profile, while “Create Layer from Outline” adds a new layer named “Outline” to the layer stack up which contains the Profile as ODB++ objects. If there is already a layer named “Outline”, all Profile objects will be added to this layer.


“Add/Set from Selection Middle” is similar to “Add Selection Outline”, but it emanates from the middle of the selection. Therefore, it is essential that the selection comprises of several objects with a closed contour. The difference between “Add” and “Set” consists in Add adding the selection to the Profile and Set replacing it.

Template layers of printed curcuit boards have to represent huge amounts of detailed information. Therefor it is not surprising that they often are not defined sufficiently large. In these cases the PCB supplier has to enlarge each and every object on all template layers, a tremendous task which is greatly simplified through the use of PCB-Investigators "Generate Oversize".

The Oversize Options offer two possibilities to enlarge or shrink template layers: one is through fixed values the other through percentage which both can be applied to any number of objects like surfaces, lines and arcs. It is also possible to work on multiple levels simultaneously.

Please be advised that there is a high possibility of holes, indentations and similar to literally grow together when using enlarge for several times as the spaces get smaller with every increase until they disappear completely (cf. image 4 below).

When the copper is not applied evenly, it can lead to twists and bow on a printed circuit board because of thermal load in production. Check first with the PCB-Investigator if danger zones exist - for individual nets, layers or the entire board!
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